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Nu Advisory Partners

CPU Frontend Design Engineer, Google Cloud



Software Engineering, Design
Tel Aviv-Yafo, Israel
Posted on Tuesday, May 23, 2023

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.


Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  • Experience in full VLSI design cycle.
  • Experience in RTL implementation of low power designs.
  • Experience in VLSI development with Verilog, SystemVerilog, System Verilog Assertions (SVA), or VHDL, and with design verification, synthesis, timing/power analysis, and DFT.

Preferred qualifications:

  • Experience in four or more SoC cycles.
  • Knowledge of modern high-performance CPU architecture and micro-architecture.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a CPU Front-End Design Engineer, you will take part in central processing unit (CPU) development, one of the most complex and critical blocks of Google’s future sever System on a Chip (SoC). You will be responsible for microarchitecture, RTL design and implementation of core technology as part of Google’s data center SoC products. You'll collaborate closely with architecture, verification, and physical design engineers, creating micro architectural definitions with RTL coding and running block level simulations.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.


  • Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).
  • Define the CPU block level design document such as interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.
  • Perform RTL development process (e.g., coding and debug in Verilog, SystemVerilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks.
  • Contribute to the SoC level integration, and participate in synthesis, timing/power closure, and silicon bring-up.
  • Participate in test plan and coverage analysis of the block and SoC-level verification.

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At Google, we’re committed to building a workforce that is more representative of the users we serve and creating a culture where everyone feels like they belong. To learn more about our diversity, equity, inclusion commitments and how we’re building belonging, please visit our Belonging page for more information.

We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.