Formal Verification Engineer, Silicon
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 4 years of experience with SystemVerilog and SystemVerilog Assertion.
- Experience with formal model checking for Application-Specific integrated circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs).
Preferred qualifications:
- Master's degree in Electrical Engineering or Computer Science with 2 years of relevant experience, or PhD in Electrical Engineering or Computer Science.
- Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, 360-DV.
- Knowledge of model checking, formal verification algorithms and formal sign-off.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
In this role, you will develop the next generation interconnect and platform solutions that scale across all of Google Silicon offerings.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the formal verification strategy, create the properties and constraints for complex digital design blocks.
- Contribute improvements to methodologies to enhance formal verification results.
- Build and implement reusable formal verification components.
- Utilize formal property verification tools combined with formal verification closure techniques to verify properties and resolve difficult to verify properties.
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