Design Verification Engineer, Devices and Services
- Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience.
- 3 years of experience in leading verification of digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
- Experience in leading verification of digital logic at RTL level using SystemVerilog or C/C++
- Master's degree in Electrical Engineering or Computer Science with 3 years of relevant experience, or PhD in Electrical Engineering or Computer Science
- Experience in Architectural background in one or more of the following (e;g, Interconnects, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, Packet Processors)
- Experience with one ore more Interconnect Protocols (eg. AHB, AXI, ACE, CHI, CCIX, CXL)
- Experience with performance verification of SOCs, SystemC, pre-Silicon analysis and post-Silicon correlation
- Experience with building verification methodologies that span simulation, emulation and FPGA prototypes
- Experience in building and leading verification teams
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
In this role, you will work on the verification of the foundation of Google SOC offerings. You collaborate with hardware architects and design engineers for functional and performance verification of the interconnect, cache coherency and memory consistency. You will also work on developing high performance VIPs for protocols supported by our interconnect, and closely collaborate in the deployment of the verification stack across a set of IPs.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Define strategy, methodology and plan the verification of the next generation configurable interconnects and memory subsystems
- Be the primary point of contact for IP DV and drive cross functional efforts with subsystem and SOC DV teams
- Provide technical guidance to the team, coordinate verification efforts with IP architecture, design and software teams
- Produce development of cross language tools and scalable verification methodologies
- Identify verification holes and to show progress towards tape-out.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
At Google, we’re committed to building a workforce that is more representative of the users we serve and creating a culture where everyone feels like they belong. To learn more about our diversity, equity, inclusion commitments and how we’re building belonging, please visit our Belonging page for more information.
We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.
Something looks off?