Design Verification Engineer, Machine Learning
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 4 years of experience verifying digital IP and subsystems.
- Experience verifying digital logic at RTL using SystemVerilog for FPGAs and ASICs.
- Experience with DV test benches/environments.
- Master's degree or PhD in Electrical Engineering or Computer Science.
- Experience with Interconnect Protocols (e.g., ACE, CHI, CCIX, CXL).
- Experience in an architectural background in one or more of the following: Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, Packet Processors.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.
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