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Nu Advisory Partners

ASIC RTL Design Engineer, Networking, Google Cloud



Bengaluru, Karnataka, India
Posted on Tuesday, May 23, 2023


Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 16 years of experience with RTL development for ASIC subsystems using SystemVerilog.
  • Experience with InfiniBand, RDMA, and RoCE/iWARP and their low latency, security, and reliability principles.
  • Experience with micro architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

  • Experience designing hardware offloads for high throughput, low latency, reliability, and security.
  • Experience estimating performance by analysis, modeling, and network simulation.
  • Experience working with Software teams optimizing the hardware/software interface.
  • Experience in a procedural programming language (e.g., C++, Python, Go).
  • Knowledge of PCIe and DRAM in networking end points, Network on Chip (NoC) principles, and protocols (e.g., AXI, ACE, and CHI).
  • Understanding of queueing, Quality of Service (QoS), and packet routing for networking and RDMA.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.


  • Acquire a complex networking ASIC subsystem.
  • Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
  • Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
  • Implement designs in SystemVerilog.
  • Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

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We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.