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ASIC Power Architect, Silicon

Google

Google

IT
New Taipei City, Taiwan
Posted on Tuesday, May 23, 2023

Google welcomes people with disabilities.

Qualifications

Minimum qualifications:

  • Bachelor's degree or equivalent practical experience
  • 4 years of experience in semiconductor design and development with a focus on low power design, implementation and methodologies

Preferred qualifications:

  • Master's or PhD degree in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance or power analysis
  • Experience in power management, in-rush current, Power Distribution Network (PDN) droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floor-planning, battery technology, concurrency management and thermal management
  • Experience with full product delivery cycle - definition, architecture, design and implementation, testing, productization
  • Understanding of techniques used to manage power delivery and thermal limits in modern SoCs and systems
  • Understanding of PMICs (SMPS, LDOs), power delivery, board-level impedances, etc.

About the job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Drive peak power and voltage droop management and mitigation architectures and strategies for Google SoCs
  • Drive both pre-silicon design and post-silicon validation and tuning to optimize power and reduce design margins
  • Optimize user experience tradeoffs in the presence of peak power constraints
  • Collaborate with, influence and provide leadership across a broad cross-functional audience spanning SoC architecture, various IPs, silicon engineering, system integration, power management architects, process/foundry technology, OS and application software teams

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

At Google, we’re committed to building a workforce that is more representative of the users we serve and creating a culture where everyone feels like they belong. To learn more about our diversity, equity, inclusion commitments and how we’re building belonging, please visit our Belonging page for more information.

We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.