Hardware Systems Architect, Augmented Reality
Qualifications
Minimum qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
- 10 years of experience in definition, design, or architecture of low-power SoC compute subsystems.
- 8 years of experience with simulation, emulation, or profiling tools.
- 4 years of experience with edge deployment of machine learning models for low-power mobile products.
Preferred qualifications:
- PhD in Electrical Engineering, Computer Engineering, or a related field.
- 12 years of experience in mobile System-on-a-Chip (SoC) architecture design or SoC performance and power modeling.
- Experience creating system performance and power Key Performance Indicators (KPIs), defining test case/vector for PowerArtist and PTPX power estimation and post-silicon performance and power validation.
- Ability to work on complex cross-disciplinary systems in a team environment.
- Excellent communication skills.
About the job
The US base salary range for this full-time position is $166,000-$254,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Responsibilities
- Partner with Technology, Hardware, Software and Research teams to understand issues, drive new compute architecture from concept into prototype, and guide the transition into SoC design requirement.
- Work with IP and SoC vendors and influence IP and SoC roadmap and features for optimal power, performance and area to meet the product requirements.
- Define, simulate and model workloads performance and power for critical Power, Performance and Area trade-offs and architectural decisions.
- Provide key contributions to SoC and use case power models, compute workloads power KPI development, set power and performance goals for SoC and provide performance and power optimization tuning guide during product development.
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