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Silicon Product Test Engineer, Google Cloud

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Product, Quality Assurance

Sunnyvale, CA, USA

Posted on Wednesday, May 24, 2023

Qualifications

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in DFT specification for designs (e.g., scan diagnostics or analysis for designs such as CPU, etc.).
Experience in silicon bring-up, debug or validation of DFT features on ATE or Bench (e.g., ATPG patterns, MBIST, etc.).

Preferred qualifications:

Master's degree in Electrical Engineering, or a related field.
Experience with Scan/ATPG test development, especially with Streaming Scan Network (SSN)/Streaming Fabric techniques, or Memory BIST test development and repair scheme implementation, including BISR/BIRA and Enhanced-Stop-on-Error (ESOE) test.
Experience with MBIST, ATPG testing, or test vector generation for fault isolation and EFA/PFA sample selection.
Experience in fault modeling (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, Gate-Exhaustive, IDDQ, and other advanced fault models).

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a Silicon Product Test Engineer, you will be responsible to define, implement, and use the software, hardware, and analytics systems necessary to characterize and diagnose manufacturing test yield loss and in-field quality escapes for complex ASICs and SoCs.

In this role, you will support silicon test strategy definition, and participate in creating Design-for-Test (DFT) and Design-for-Debug (DFD) specifications for complex SoCs in advanced technologies. You are directly responsible for diagnosing memory and logic scan test failures, increasing production quality, and enhancing yield.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $146,000-$220,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Develop and execute strategies for SoC Product New Product Introduction (NPI) test, bring-up, characterization, failure diagnosis, and fault isolation, including troubleshooting, yield diagnostics, and Return Materials/Merchandise Authorization (RMA) support.
Setup and maintain test and yield analysis infrastructure, including diagnostic databases, software, and hardware for logic and memory fail debug.
Support ASIC and SoC DFT strategy, architecture, and test sequence development.
Collaborate with cross-functional teams across the globe including ATE Test Engineering, Packaging, Supply chain, and Operations to ensure high production yield and high quality in-field operation.

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