Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

As a Machine Learning ASIC Design Engineering Lead, you will provide day-to-day guidance to Silicon engineers. You and the team will be responsible for architecting, designing, and verifying digital logic using Chisel, Verilog, and/or SystemVerilog for the gChips TPU team. You will interface with architects to define features and interface with Physical Design teams to ensure efficient implementation to produce high-quality PPA. You will work with Production and Silicon Validation teams to enable chip bring-up and production test.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $172,000-$263,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Set technical direction for the team within the capacity of technical lead and people manager.
  
• Engage with Machine Learning System Architects and Software teams to define specifications and implement digital logic using Chisel, Verilog, and/or SystemVerilog.
  
• Engage with Verification and Silicon Validation teams to ensure functionality of the design.
  
• Perform power, area, and performance trade-offs of digital designs and architectures.
  
• Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.