Senior Static Timing Analysis Engineer, Devices and Services
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience in silicon timing closure and chip integration.
- Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
- Experience with static timing analysis sign-off constraints authoring for full-chip/subsystem level, tape-out sign-off requirements, checklists, and associated automation.
- Master's degree in Electrical Engineering, Computer Science, or a related field.
- Experience in the delivery of high complexity silicon in technology process nodes.
- Experience in extraction of design parameters, Quality of Results (QoR) metrics, and analyzing data trends.
- Knowledge of semiconductor device physics and transistor characteristics.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Define timing closure and Static Timing Analysis (STA), timing constraints development, and timing Engineering Change Order (ECO) using Tweaker, Prime Closure, and Distributed Multi-Scenario Analysis (DMSA).
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