Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

The US base salary range for this full-time position is $172,000-$263,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Engage with Foundry partners/third-party vendors to manage foundry PDK/DK and design library collaterals. Work with cross-functional teams on assessing DR/DRC/DFM impact and evaluate advanced technology/Foundry process readiness for product adoption.
  
• Collaborate with internal teams on assessing technology interception point based on process readiness/maturity and product roadmap needs.
  
• Review and assess Foundry silicon data against SPICE/design goals and compile SPICE to Silicon gap analysis. Drive foundry partners on CIPs to improve foundry process to meet technology entitlement and product goals.
  
• Guide internal IP/design teams on appropriate usage of technology attributes/offerings in accordance with product requirements (e.g., performance, power, area, and cost).
  
• Collaborate with internal third-party infrastructure, customization, test-chip, methodology, and packaging and product test engineering teams for seamless execution of product bring-up and productization.