ASIC Power Architect, Multimedia, Silicon
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Qualifications
Minimum qualifications:
- Bachelor's degree or equivalent practical experience
- 7 years of experience in ASIC power management or low power design/methodology
- Experience with ASIC low power flows and power management concepts
Preferred qualifications:
- Master's degree/PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance, and power analysis
- Experience with power for multimedia IPs in mobile SoCs (e.g., ISP, codecs, display processor)
- Experience with ASIC design flows from concept to post-silicon
- Experience with ASIC power modeling/estimation, defining power goals, power roll-ups, power/voltage domains design, and low power architectures/optimization techniques (e.g., clock gating, power gating, multi Vth, DVFS)
- Knowledge of the impact of software and architectural design decisions on system power and thermal behavior
- Familiarity with PMIC, SMPS, LDO, and power delivery networks
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Define and drive low power solutions for SoCs to optimize Power Performance Area (PPA) under peak current and thermal constraints with a focus on multimedia IPs (e.g., ISP, codecs, display processor, etc.).
- Define power Key Performance Indicators (KPIs) and SoC/IP-level power goals, guide architecture, design and implementation to achieve power goals, create power models, perform power roll ups, and track power throughout the design cycle.
- Propose and drive power optimizations throughout the design process from concept to mass productization.
- Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
- Perform post-silicon characterization and productization of power features.
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