Performance Engineer and CPU Architecture
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Austin, TX, USA.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience
- Experience in performance modeling, performance analysis, and workload characterization.
- Experience in general-purpose programming language (i.e., C/C++, Python)
- Experience in modern, high-performance CPU/ML architecture and micro-architecture
- Ph.D in Electrical Engineering, Computer Engineering, or Computer Science, emphasizing on computer architecture or artificial intelligence/machine learning.
- Experience with processor instruction set architecture (e.g., ARM, RISC-V, x86).
- Experience in integrating ARM cores into ASICs at architectural and RTL levels.
- Knowledgeable on system software components, such as Linux, drivers, and runtime.
About the job
The US base salary range for this full-time position is $124,000-$182,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
- Evaluate ARM’s architecture features from both architecture and performance angles
- Develop performance model for performance analysis and micro-architecture study
- Project, analyze, and debug pre-silicon and post-silicon application performance
- Work with CPU architect to determine CPU subsystem architecture specifications
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