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Nu Advisory Partners

SoC Interface Architect



New Taipei City, Taiwan
Posted on Wednesday, May 24, 2023

Google welcomes people with disabilities.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Banqiao District, New Taipei City, Taiwan; Xindian District, New Taipei City, Taiwan.


Minimum qualifications:

  • Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
  • 5 years of experience with low speed or high speed interface IP/systems design or architecture.

Preferred qualifications:

  • Master's degree in Computer Science or Electrical Engineering.
  • 8 years of experience with USB architecture, micro-architecture, design, and integration.
  • Experience with low speed IO such as SPMI, I3C, SPI, UART, I2C, I2S, TDM, PDM, SoundWire and/or GPIO controller.
  • Experience with or desire to learn other high speed IOs such as DisplayPort, UFS, PCIe, SD, and/or eMMC.
  • Knowledge of USB2 and USB3 standards and related specifications.

About the job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

In this role, you'll be responsible for the architectural definition/configuration of the IO subsystems of SOC products. You'll collaborate with Software and Hardware Architects to build a compelling, set of interfaces, and justify your decisions with the performance of relevant workloads and use-cases. Utilizing your standards-specific knowledge, you will support the configuration and integration of IPs into the overall design, including working with the power, clock, fabric, security, system, and all other related architects.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.


  • Define the USB and Low Speed IO interface architecture of future SOCs and author the architecture and microarchitecture specifications.
  • Collaborate with company-wide stakeholders like Product Management, System Architecture, and Software Engineering to develop USB and Low-Speed IO interface roll-up and features.
  • Understand device usage scenarios and help drive performance, power, area (PPA) tradeoff evaluation of prospective IPs and sub-systems.
  • Work closely with Design, Verification, Physical Design, and Silicon Validation teams to ensure the implementation follows the architectural and micro-architectural intent.
  • Monitor relevant industry and academic trends and contribute to relevant standards bodies.

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At Google, we’re committed to building a workforce that is more representative of the users we serve and creating a culture where everyone feels like they belong. To learn more about our diversity, equity, inclusion commitments and how we’re building belonging, please visit our Belonging page for more information.

We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.