ASIC Design Verification Engineer
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Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Xindian District, New Taipei City, Taiwan; Banqiao District, New Taipei City, Taiwan.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- Experience verifying digital logic at RTL using SystemVerilog for FPGAs or ASICs.
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Experience creating and using verification components and environments in standard verification methodology.
Preferred qualifications:
- Master's or PhD degree in Electrical Engineering or Computer Science.
- 3 years of design verification experience.
- Experience with image processing, computer vision, and/or machine learning applications.
- Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
- Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
- Experience with verification techniques.
About the job
In this role, you will be part of a Research and Development team, and you will build verification components, use constrained-random testing, end-to-end system testing, and verification closure.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and UVM, or formally verify designs with SVA and formal tools.
- Identify and write coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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