Technical Lead, Devices and Services, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 5 years of experience working in hardware engineering.
- Experience in Verilog or System Verilog language.
Preferred qualifications:
- Experience in high-performance design, multi power domains with Complex clocking, and multiple SoCs with silicon success.
- Experience in design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation.
- Knowledge of chip design flow and cross domain including DV/DFT/Physical Design/Software.
- Knowledge of one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
- Ability to participate in STA closure, DV test-plan and coverage analysis of the sub-system and chip level verification.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Lead a team of ASIC RTL engineers on Sub-system and chip-level Integration activities including, plan tasks, hold code and design reviews, code development of complex features.
- Interact with the Architecture team and develop implementation strategies to meet quality, schedule and Performance, Power, Area (PPA) for Sub-system/chip-level integration.
- Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
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Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.
This job is no longer accepting applications
See open jobs at Google.See open jobs similar to "Technical Lead, Devices and Services, Silicon" ASU+GSV Summit.