Design Verification Engineer, Devices and Services
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See open jobs at Google.See open jobs similar to "Design Verification Engineer, Devices and Services" ASU+GSV Summit.Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, Mechanical Engineering, Software Engineering, related technical field, or equivalent practical experience.
- Experience verifying digital logic at RTL using SystemVerilog for FPGAs or ASICs.
- Experience verifying digital IP and subsystems.
- Experience with DV Tesbenches/environments.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science.
- Experience with a scripting language such as Python or Perl.
- Experience with performance, low power verification of SoCs or IP components.
- Experience with ambient computing, low power, security or machine learning applications.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As an ASIC Design Verification Engineer, you will be part of a Research and Development team verifying IPs, SoCs, AI/Machine Learning, ambient computing, low power, security, and more. You will build verification components, constrained-random testing, system testing, and verification closure.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $105,000-$152,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM or formally verify designs with SVA and industry leading formal tools.
- Identify and create types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.
This job is no longer accepting applications
See open jobs at Google.See open jobs similar to "Design Verification Engineer, Devices and Services" ASU+GSV Summit.