Hardware Engineer, Complementary Metal-Oxide-Semiconductor Foundation
- Bachelor’s degree in Computer Engineering or equivalent practical experience.
- 7 years of experience in designing and drawing layouts of high-speed/low power memories or standard-cells.
- Experience in drawing layout for sense amplifiers, decoders, assist circuits, latches, flip-flops, isolation cells, power switches, and level shifters.
- Experience generating Library Exchange Format (LEF) and views.
- Experience in skill coding, sed, awk, and Unix shell scripting.
- Experience mentoring and leading vendor layout engineers.
- Understanding of layout design rules, layout dependent effects, and Design for Manufacturing (DFM) in advanced Fin Field-Effect Transistor (FinFET) technology nodes.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Understand transistor level layout design to optimize SRAM memory and standard-cells PPAC.
- Manage circuit block placement, route planning, and integration of memory (6T, 8T, 10T, 12T) arrays into subsystems.
- Perform transistor level layout of decoder, assist, and column input/output blocks.
- Perform transistor level layout of new standard-cell topologies.
- Understand block level DRC, LVS, EM, Antenna verification flows.
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Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.
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