SoC DFT Engineer
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in DFT specification for designs (e.g., CPU, GPU, Networking).
- Experience in silicon bring-up, debug, or validation of DFT features on ATE or bench (e.g., ATPG patterns, MBIST, I/JTAG, etc.).
Preferred qualifications:
- Master's degree in Electrical Engineering.
- Experience architecting chip-level DFT solutions, IP integration (e.g., memories, Test controllers, TAP, MBIST), and/or ASIC DFT, synthesis, simulation and/or verification flows.
- Experience using EDA Test tools (e.g., DFT Max, SpyGlass, Tessent etc.).
- Experience in fault modeling (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, Gate-Exhaustive, IDDQ, and other advanced fault models).
- Knowledge of various Test standards (e.g., IEEE 1149.1, 1149.6, 1500, 1687), test formats (e.g., BSDL, ICL, PDL, STIL, CTL).
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
As a DFT Engineer, you will define, implement and deploy advanced Design-For-Test (DFT) methodologies for complex digital and/or mixed-signal chips and/or IPs. You will define silicon test strategies, DFT architecture, and create DFT and Debug specifications for complex next generation SoCs. In this role, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and reducing test cost.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $146,000-$220,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG) and Joint Test Action Group (JTAG), and associated boot up and execution sequences.
- Complete all test design rule checks and design changes.
- Drive DFT logic, including boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.
- Drive MBIST logic including test collar around memories, MBIST controllers, eFuse logic and connect to core and TAP interfaces.
- Develop diagnostic databases, software and hardware, for logic and memory fail debug.
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