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Nu Advisory Partners

Circuit Design Engineer, Technical Infrastructure



IT, Other Engineering, Design
Sunnyvale, CA, USA
Posted on Friday, May 26, 2023


Minimum qualifications:

  • Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
  • 5 years of experience with circuit and physical design disciplines involving advanced process technology nodes.
  • Experience with concurrent optimization across custom circuit/IP and physical design spaces.
  • Experience with Power, Performance, and Area design trade-offs and optimizations.

Preferred qualifications:

  • Master's degree in Computer Science, Electrical Engineering, or a related field.
  • Experience with running industry standard tools for synthesis, place and route, and static timing analysis, transistor level design in advanced finfet technology nodes, including SPICE simulations.
  • Experience with delivering optimized custom circuits, memories, IPs, and/or digital place-and-route blocks leading to product tapeouts.
  • Experience with programming/scripting (e.g., TCL, Python, and/or Perl).
  • Understanding of characterization and verification of standard cells/static RAMs/register files, including power, noise, and IR analysis.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a Circuit Design Engineer, you will collaborate with circuit design, physical design, technology, and hardware architecture leads to overcome the slowing of Moore’s Law and deliver cutting edge ASIC’s and SoC’s. You will drive best product Power, Performance, and Area (PPA) by optimizing across technology nodes, circuit design, memories, digital block implementation, clock distribution, floorplanning, and third-party IPs. You will drive new and novel methodologies that co-optimize across the entire design space, and see these through from inception to maturity and tapeout. As part of this work, you will participate in the development of exceptional technology in high-performance computing and file associated patents.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $146,000-$220,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.


  • Optimize digital blocks for performance, power, area, and reliability using circuit and physical design techniques.
  • Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization.
  • Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.
  • Work with our Circuits, Physical Design, Technology, and Architecture teams and IP partners in advanced CMOS nodes.

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At Google, we’re committed to building a workforce that is more representative of the users we serve and creating a culture where everyone feels like they belong. To learn more about our diversity, equity, inclusion commitments and how we’re building belonging, please visit our Belonging page for more information.

We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.