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SoC Interface Architect

Google

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New Taipei City, Taiwan

Posted on Tuesday, June 27, 2023

Google welcomes people with disabilities.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Banqiao District, New Taipei City, Taiwan; Xindian District, New Taipei City, Taiwan.

Qualifications

Minimum qualifications:

Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
5 years of experience with low speed or high speed interface IP/systems design or architecture.

Preferred qualifications:

Master's degree in Computer Science or Electrical Engineering.
8 years of experience with USB architecture, micro-architecture, design, and integration.
Experience with low speed IO such as SPMI, I3C, SPI, UART, I2C, I2S, TDM, PDM, SoundWire and/or GPIO controller.
Experience with or desire to learn other high speed IOs such as DisplayPort, UFS, PCIe, SD, and/or eMMC.
Knowledge of USB2 and USB3 standards and related specifications.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

In this role, you'll be responsible for the architectural definition/configuration of the IO subsystems of SOC products. You'll collaborate with Software and Hardware Architects to build a compelling, set of interfaces, and justify your decisions with the performance of relevant workloads and use-cases. You will support the configuration and integration of IPs into the overall design, including working with the power, clock, fabric, security, system, and all other related architects.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Define the USB and Low Speed IO interface architecture of future SOCs and author the architecture and microarchitecture specifications.
Collaborate with company-wide stakeholders like Product Management, System Architecture, and Software Engineering to develop USB and Low-Speed IO interface roll-up and features.
Understand device usage scenarios and help drive performance, power, area (PPA) tradeoff evaluation of prospective IPs and sub-systems.
Work closely with Design, Verification, Physical Design, and Silicon Validation teams to ensure the implementation follows the architectural and micro-architectural intent.
Monitor relevant industry and academic trends and contribute to relevant standards bodies.

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