Minimum qualifications:

• Bachelor's degree in Computer Engineering, Electronics, or equivalent practical experience.
  
• 4 years of experience in Verilog and developing verilog models for standard cells and memories.
  

Preferred qualifications:

• Knowledge of adjacent domains like GLS/Emulation.
  
• Understanding of DFT features like BIST, ATPG, and SCAN.
  
• Proficiency in front-end quality checks (LINT, CDC) and UPF generation.
  
• Proficiency with chip design flow.