Minimum qualifications:

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  
• 15 years of experience in ASIC design implementation flows.
  
• Experience in driving execution for low-power physical design implementation with industry standard synthesis and Static Timing Analysis (STA) tools.
  
• Experience in sign-off convergence including STA, electrical checks, and physical verification.
  

Preferred qualifications:

• 5 years of experience with CPUs and leading processor Physical Design teams.
  
• Experience in programming and scripting languages such as Python, TCL, or Perl.
  
• Experience with metric driven Performance Power Area (PPA).
  
• Experience in CPU implementation, including critical timing and power fix iterations with RTL and Micro architecture teams.