ASIC Engineer, Static Timing Analysis
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Posted 6+ months ago
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 8 years of experience with Static Timing Analyses, sign-off corner definitions, process margining, and set up of frequency goals with technology scaling and platform development kit (PDK) changes.
- Experience with liberty timing models and Static Timing Analysis tools (e.g., Primetime, Tempus).
Preferred qualifications:
- Understanding of the basics of circuit and standard cell design.
- Understanding of the fundamentals of computer architecture.
- Understanding of synthesis, PnR, and power performance area (PPA) optimizations.
This job is no longer accepting applications
See open jobs at Google.See open jobs similar to "ASIC Engineer, Static Timing Analysis" ASU+GSV Summit.