ASIC Design Verification Engineer, Machine Learning
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Sunnyvale, CA, USA
Posted 6+ months ago
Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
- Experience with SystemVerilog (e.g. SystemVerilog Assertions or functional coverage).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering.
- Experience with Universal Verification Methodology (UVM).
- Experienced with the full verification life cycle.
This job is no longer accepting applications
See open jobs at Google.See open jobs similar to "ASIC Design Verification Engineer, Machine Learning" ASU+GSV Summit.