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Multimedia Design Verification Engineer, Silicon



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Marketing & Communications, Design
New Taipei City, Taiwan
Posted on Tuesday, February 13, 2024

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Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
  • Experience verifying digital logic at RTL using SystemVerilog for ASICs.
  • Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
  • Experience with object oriented programming.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering or Computer Science with 3 years of relevant work experience.
  • Experience creating and using verification components and environments in a standard verification methodology such as UVM.
  • Experience with image processing or other multimedia IPs such as Display or Video Codec.
  • Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
  • Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
  • Experience with GLS, low-power DV, and support of SOC DV.

This job is no longer accepting applications

See open jobs at Google.