Minimum qualifications:

• 10 years of experience in DFT specification definition architecture and insertion.
  
• Experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent).
  
• Experience with ASIC DFT synthesis, STA, simulation, and verification flow.
  
• Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
  

Preferred qualifications:

• Master's degree in Electrical Engineering.
  
• Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
  
• Experience in SoC cycles, including silicon bring-up and silicon debug activities.
  
• Experience in fault modeling.