TPU ASIC Design Verification Engineer, Machine Learning
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Sunnyvale, CA, USA
Posted on Tuesday, February 13, 2024
Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
- 3 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with SystemVerilog (i.e. SystemVerilog Assertions or functional coverage).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering.
- 6 years of work experience with full verification life cycle.
- Experience verifying digital logic at RTL using SystemVerilog for ASICs.
- Experience in Power aware verification, Gate level simulations, and Post silicon bring-up.
- Strong problem solver, communicator and team player.
This job is no longer accepting applications
See open jobs at Google.See open jobs similar to "TPU ASIC Design Verification Engineer, Machine Learning" ASU+GSV Summit.