Minimum qualifications:

• Bachelor's degree in Computer Engineering, Electronics, or equivalent practical experience.
  
• 4 years of experience in Verilog and developing verilog models for standard cells and memories.
  

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Science, or a related field.
  
• Experience in micro-architecture and coding in one or more of these areas: coherence, cache design, AXI, ACELITE, APB.
  
• Experience with ASIC design methodologies for clock domain checks and front quality checks (e.g., Lint, CDC/RDC, Synthesis, UPF, and Low Power Optimization/Estimation).
  
• Understanding of cross-domain involving domain validation, design for testing, physical design, and software.