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SoC Full Chip Timing and Physical Design Lead

Google

Google

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Design
Bengaluru, Karnataka, India · Karnataka, India
Posted on Tuesday, February 13, 2024

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
  • 4 years of experience in physical design in the industry.
  • Experience in ECO (Engineering Change Order) flows for sign-off timing convergence.
  • Experience with PD (Physical Design) tools like Innovus and Fusion Compiler.
  • Experience with STA (Static Timing Analysis) tools like primetime or tempus.

Preferred qualifications:

  • Experience in the delivery of high performance silicon in latest technology process nodes.
  • Experience in extraction of design parameters, QoR metrics and analyzing data trends.
  • Experience and understanding in engineering across timing analysis, physical design and high level implementation.
  • Experience in overall Physical Design and Full-chip Timing closure with latest technologies.
  • Knowledge of semiconductor device physics and transistor characteristics.

This job is no longer accepting applications

See open jobs at Google.