Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• Experience with RTL design using Verilog/System Verilog.
  
• Experience with a scripting language (e.g., Python or Perl).
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with ARM-based SoCs, interconnects, and ASIC methodology,
  
• Experience with methodologies for low power estimation, timing closure, and synthesis.
  
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
  
• Experience with IP design for clocking, interconnects, and peripheral.