Chip Package Signal and Power Integrity Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of industry experience in the SI/PI field.
- Experience in chip package SI/PI design for interconnections and advanced package design.
Preferred qualifications:
- Experience in post silicon correlation with models.
- Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
- Experience in cross-functional collaboration with chip top design, physical design, STA, package, system design, and validation teams.
- Experience in programming and data analysis with Matlab, Python, C++ and statistical tools to establish automation flows and data processing.
- Understanding of on and off chip power delivery and STA/voltage budget.
- Familiarity with memory testing, next generation memory, chiplet standards and timing budget methodology.
About the job
As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package and system level.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Contribute to chip-package-system co-design by performing Signal Integrity (SI)/Power Integrity (PI) analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for High Performance Computing (HPC) based on 2.5D/3D package technology.
- Develop next generation IO interfaces (serdes, memory, D2D) considering IO PHY, SI/PI and physical design.
- Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design target, unleash boundaries of chip performance and explore SI/PI and DFM tradeoff for advanced package design closure for production.
- Provide feedback on chip floorplan considering IP performance/package/system routability and SI/PI.
- Conduct post silicon validation and qualification of high speed interface for NPI.
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This job is no longer accepting applications
See open jobs at Google.See open jobs similar to "Chip Package Signal and Power Integrity Engineer" ASU+GSV Summit.