SoC Design Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 2 years of experience with RTL coding using Verilog/SystemVerilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

Preferred qualifications:

• Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL.
  
• Experience with SOC implementation standards and interfaces (e.g. AXI).
  
• Experience as a design lead or technical management of RTL engineers.
  
• Experience with scripting languages (e.g., Tcl, Python or Perl).
  
• Strong understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.

About the job

In this role, you will join a team working on SoC-level RTL design for our data center accelerators. You'll own RTL, architecture, design, and implementation of global communication busses, and integration of complex ASIC designs. This is a cross-functional and central role that will require interactions with numerous ASIC development teams. You will own deliverables to the cross-functional teams (e.g., Physical Design, Verification, Validation, Firmware) at various project milestones. You will also be involved in defining and creating methodologies that enable a highly efficient design environment for all ASIC engineers.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Develop strategies for system segmentation to enable programmatic assembly of custom solutions based off user design intent.
• Design RTL architecture of system to allow for automated optimization of RTL performance, power, and area based off of solution requirements.
• Provide mentorship and guidance for a team of 6 RTL designers.
• Design and implement RTL code for various digital blocks, including control logic, and on-chip data paths.
• Contribute to the development and improvement of design flows, tools, and methodologies.