ASIC Design Engineer, Platform IP, Silicon

corporate_fareGoogleplaceMountain View, CA, USA

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to improve RTL code, performance and power as well as low-power design techniques.
• Experience with ARM-based SoCs, interconnects and ASIC methodology.
• Experience with a scripting language like Python or Perl.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 3 years of experience with Intellectual Property (IP) design for clocking, interconnects or peripherals.
• Experience with methodologies for low power estimation, timing closure, or synthesis.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Our team takes pride in our ability to transform algorithms and processes into a user-friendly form. If you are someone who enjoys crafting tools to empower other creative people then this is the right job for you.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
• Perform RTL development (SystemVerilog), debug functional/performance simulations.
• Perform RTL quality checks including Lint, Critical Dimension Control, Synthesis, Unified Power Format checks.
• Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
• Communicate and work with multi-disciplined and multi-site teams.